pub const FDDMA_CTL: usize = 0x0;
pub const FDDMA_CHAN_0_3_CFG: usize = 0x4;
pub const FDDMA_STA: usize = 0x8;
pub const FDDMA_MASK_INTR: usize = 0xC;
pub const FDDMA_CHAN_4_7_CFG: usize = 0x28;

#[inline(always)]
pub const fn FDDMA_CHAN_DDR_UP_ADDR(ch: usize) -> usize { 0x40 + 0x40 * ch }
#[inline(always)]
pub const fn FDDMA_CHAN_DDR_LOW_ADDR(ch: usize) -> usize { 0x44 + 0x40 * ch }
#[inline(always)]
pub const fn FDDMA_CHAN_DEV_ADDR(ch: usize) -> usize { 0x48 + 0x40 * ch }
#[inline(always)]
pub const fn FDDMA_CHAN_TS(ch: usize) -> usize { 0x4C + 0x40 * ch }
#[inline(always)]
pub const fn FDDMA_CHAN_CTRL(ch: usize) -> usize { 0x58 + 0x40 * ch }

pub const FDDMA_CTL_ENABLE: u32 = 1 << 0;
pub const FDDMA_CTL_SRST: u32 = 1 << 1;

#[inline(always)]
pub unsafe fn write_reg32(base: *mut u8, off: usize, val: u32) {
    (base.add(off) as *mut u32).write_volatile(val);
}

#[inline(always)]
pub unsafe fn read_reg32(base: *mut u8, off: usize) -> u32 {
    (base.add(off) as *const u32).read_volatile()
}


